(1) Field of the Invention
This invention relates generally to the field of DC-to-DC converters and relates more specifically to switched power supplies converters having a programmable input current limit and a controlled limited output current in order to operate with maximum efficiency and providing a regulated power supply to battery equipped systems. The power supply is required to provide the charge current to the battery while, at the same time, being able to deliver current to the system.
(2) Description of the Prior Art
Buck or Boost Converters find extensive use in power management applications because of their high efficiency. They can step up or down an input voltage source to a different voltage supply DC level more appropriate for a specific load.
They use a storage element device (an inductor) on which energy is alternatively stored and then delivered to a load. At this purpose switches are used, whose ON and OFF states are defined by the high and low times of a usually fixed frequency digital control signal. It is common practice to implement a closed loop solution which adapt the duty cycle of the digital control signal in such a way to maintain a constant DC voltage at the output over a wide range of a system current requirements.
FIG. 1 illustrates the basic layout of a prior art buck converter. It comprises a DC voltage source Vin, a first switch S1, a second switch S2, an inductor L (as energy storage element) and an output capacitor C to filter the output voltage Vout. The control circuitry 1 receives as input a constant frequency Clk signal and a reference voltage Vref and, as feedback, the output voltage ΔΣlt generates gate drive control signals for the switches S1 and S2, which are synchronous to the Clk, i.e. they have constant frequency, but whose duty cycle is adjusted in such a way that the output voltage Vout tracks the reference voltage Vref for a wide range of system loads and/or input supply fluctuations. The operation of the buck converter of FIG. 1 is described also with reference to FIG. 3 where the Clk signal, the current through the inductor IL and the gate control signal are also shown in steady state conditions. The switch S2 is turned on (and correspondingly the switch S1 is turned off) at constant frequency, synchronously to the input clock signal, there by connecting the voltage source Vin to the inductance L. The current IL rises linearly with a slope
            Vin      -      Vout        L    .Within the clock period the switch S2 is turned off (and correspondingly the switch S1 turned on), thereby connecting the inductance to Ground. In this phase the current IL decreases linearly with a slope
      Vout    L    .In steady state condition the following condition must hold
                              Vin          -          Vout                L            ⁢      Ton        =                  Vout        L            ⁢      Toff        ,leading therefore to the following relationship
  Vout  =            Ton      T        ⁢          Vin      .      The output voltage Vout depends from the duty cycle of the gate control signal, the input supply voltage Vin and, even if not explicitly apparent from this first order analysis, from the output load Isys, i.e. a current supporting a system load.
In order to keep the output voltage Vout tracking a given reference voltage Vref, the control circuitry 1 varies the duty cycle of the gate control signal. This can be done in a number ways: generally the control loop provides a voltage Verror, as shown in FIG. 8 prior art, which is proportional to the difference between Vout and the reference Vref. This voltage is then compared to a ramp signal with a saw-tooth waveform, to generate a PWM signal, which then controls the status of switches. The ramp signal can be a constant signal (voltage mode control) or it may be proportional to the inductor current IL (current mode control).
FIG. 8 prior art shows a particular implementation of a current mode control buck converter. In this scheme the voltage/current feedback loop provided by the amplifier 81 and the PWM comparator 80 regulates the output duty-cycle in such a way that output voltage Vout tracks reference voltage Vref. In particular the main switch 83 is turned-on at the beginning of each clock cycle. It is only turned off when the positive input of the PWM comparator 82, which is proportional to the output current, exceeds the error voltage Verror.
A desirable feature of a DC-DC converter is a peak current limitation capability by which the current drawn from the input power supply Vin is confined below a (usually programmable) target value at any time. This property is essential in particular when dealing with output limited power supply, i.e. USB input, and to protect the regulator's component and the system load from an excessive current flow.
In the current practice a cycle-by-cycle current limit scheme is implemented: at each cycle of an external clock signal the current in the supply path is sensed and compared to a reference. Whenever its value exceeds this reference, the power converter high side switch is turned off instantaneously. It will be again turned on in the next clock cycle.
In the architecture of FIG. 8 prior art, the current limit is implemented comparing the drain source voltage Vsw of the main switch 83 with a drain source voltage Vsw—ref of a scaled matched device 84 through the comparator 80. If M is the scaling factor of the main switch 83 related to the device 84, this comparator will toggle when input current Iin>Iref multiplied by scaling factor M, wherein Iref is a reference current which can be externally set by a current source. In this condition the SR-latch 85 will be reset, thereby turning off the main switch 83 and turning on the synchronous rectifier 87. The comparator 80 is reset in the next clock cycle.
In current limit conditions the output duty cycle is not determined anymore by the voltage/current feedback loop provided by the amplifier 81 and the PWM comparator 82, but by the comparator 80. The high side power switch 83 can be turned off at any time within the clock period independent of the PWM comparator output. As shown in FIG. 3 this leads to an unsteady behavior of the output current IL characterized by the presence of sub-harmonics of the clock frequency (which could interfere with other system's component), an increased ripple which leads to more power losses and less efficiency, a reduced maximum average power deliverable to the load.
DC-DC converters are widely used in battery equipped system such that of FIG. 4 to provide current both to the battery and the system. While the system requirements are normally unpredictable and heavily user's dependent, the charge current is normally settable from the system itself. It would be highly desirable in this case, and in general in any case a fraction of the DC-DC converter output current is controllable by a system host, to have a mechanism which automatically reduce the charge current before the buck converter enters current limit conditions and this for the largest possible range of load current requirements.
There are patents or patent publications dealing with the operation of buck converters:
(U.S. Pat. No. 7,365,526 to Cha et al.) discloses a synchronous buck DC/DC converter performing an improved switching operation by adjusting a variable resistor is provided. The synchronous buck DC/DC converter includes a switching unit for switching two PWM signals inverted with a dead time and outputting the PWM signals, a smoothing circuit for outputting DC power using a waveform output from the switching unit as an input, a variable resistor connected to the switching unit and adjusting a switching time of the waveform output from the switching unit, and a variable resistor controller for sensing a current from an output terminal of the smoothing circuit and setting the resistance of the variable resistor to a resistance corresponding to the sensed current.
(U.S. Pat. No. 7,235,955 to Solie et al.) proposes a controllably alternating buck mode DC-DC converter conducting cycle by cycle analysis of the direction of inductor current flow to decide whether to operate in synchronous buck mode or standard buck mode for the next successive cycle. For each cycle of the PWM waveform controlling the buck mode DC-DC converter, a mode control circuit examines and latches data representative of the direction of inductor current flow relative to the chargeable battery. If the inductor current flow is positive, a decision is made to operate in synchronous buck mode for the next PWM cycle, which allows positive current to charge the battery; if the inductor current drops to zero, a decision is made to operate the converter in standard buck mode for the next PWM cycle, so as to prevent current from flowing out of the battery and boosting the system bus.
(U.S. Pat. No. 7,035,071 to Tiew et al.) discloses a switching regulator having a current limit with adaptive cycle skipping. A buck type switching regulator circuit is provided, including an energy storage component, such as an inductor or capacitor, and a switch for controllably providing an input current to the energy storage component. A control unit controls the on time and the off time of the switch by providing cyclically recurring control pulses to the switch that cause the switch to be on during the pulses and off otherwise. A current monitor circuit monitors a current corresponding to the input current applied to the energy storage component during the periodic control pulses. An overcurrent signal generator generates an overcurrent signal pulse upon detection of the monitored current at a level above a predetermined level corresponding to an overcurrent condition. A state machine responds to the overcurrent signal pulse and suppresses a number of the cyclically recurring control pulses, thereby controlling the period between the recurring control pulses that are not suppressed, in accordance with a predetermined algorithm that increases the number each time an overcurrent signal pulse is detected in successive periods.
(U.S. Pat. No. 7,019,507 to Dittmer et al.) discloses methods and circuits for protecting power converters from over-current conditions that, in one embodiment, (1) reduce average inductor current to a steady-state threshold during a transient phase and regulate average inductor current in steady-state regulation approximately at the steady-state threshold; and (2) reduce instantaneous inductor current after the instantaneous inductor current exceeds a maximum instantaneous threshold during the transient phase.
Furthermore Texas Instruments has published an application note “Fully Integrated Switch-Mode One-Cell Li-Ion Charger with Full USB compliance and USB-OTG support” describing a charge management device for single cell batteries, wherein charge parameters can be programmed through an I2C interface. The bQ24150/1 charge management device integrates a synchronous PWM controller, power MOSFETs, input current sensing, high accuracy current and voltage regulation, and charge termination, into a small WCSP package.